ModelSim Tutorial

1. Introduction

2. Introduction

3. Beginners' Guide

In the compilation phase all syntactical bugs/typos will be pointed out. After you have succesfully managed to compile the design, actual simulation/debugging of semantical mistakes (= design errors) may begin. (In fact ModelSim may point out some possible design pitfalls already in compilation phase.)

You can manage your VHDL libraries with following shell commands. Study them carefully:

vlib      Create a new library
vmap      Map physical and logical library
vdir      List currently compiled design units
vdel      Delete a design unit
vmake     Automatically generate Makefile

vcom      Compile VHDL source code
vsim      Simulate compiled design

4. Exercises and demos

First we need a VHDL library where we can compile our source code.

Create two libraries (codelib and traffic_lib)

   % vlib codelib
   % vlib traffic_lib
   

Now we must tell ModelSim where our newly created libraries are located in physical media (= path on the disk we are using).

Map the physical and logical library

   % vmap codelib $PWD/codelib
   % vmap traffic_lib $PWD/traffic_lib
   

$PWD here represents full path to the physical library.

Hint: If you use only vmap without parameters you will get a list of currently mapped libraries, which ModelSim.ini you are currently using and physical location of every library.

Download following vhdl files:
• package.vhdl
• behavioral.vhdl
• top_level_entity.vhdl

Compile the vhdl package into the traffic_lib:

   % vcom package.vhdl -work traffic_lib -source
   

-work path
Specify library WORK

-nowarn #
Do not flag warnings for the warning number specified.

-line #
Specify starting line number

-source
Print the VHDL source line with error messages

-just e,a,p,b,c
Compiles only the specified units (entities, architectures, package headers, package bodies, configurations)

-skip e,a,p,b,c
Compiles everything except the specified units (entities, architectures, package headers, package bodies, configurations)

% vmap destination_library work

Map the work to codelib and compile the architecture and entity into it.

Map the work into codelib:

   % vmap work codelib
   

Try now vmap...

   % vmap
   
   Reading /home/user/.ModelSim.ini
   "work" maps to directory codelib.
   "codelib" maps to directory /home/user/codelib.
   ...
   

Verify that you mappings are something like above. After that you can compile the source code into codelib...

   % vcom top_level_entity.vhdl -source
   % vcom behavioral.vhdl -source 
   

Generate a Makefile from the codelib's sources:

   % vmake codelib > Makefile
   

More information about make and Makefile from UNIX manuals (% man make) See also: man touch.

Now you are ready to simulate out traffic lights!

Start ModelSim

   % vsim
   

There are two ways to give commands to ModelSim. You can either choose commands with mouse from simulator's GUI or write them directly to the command line. Try for example writing:

VSIM> view variables 

You can also write scripts and then execute them by choosing (ModelSim : Macro - Execute Macro...)

Simulation

View the wave -window by choosing (ModelSim : View - Signals) and (Signals : Wave - Signals) in region or by writing to the command line:

   VSIM> add wave *
   

You can force signals from (Signals : Force - Force...) or by writing commands to the command line:

   VSIM> force -deposit /clk 1 5 -repeat 20
   VSIM> force -deposit /clk 0 10 -repeat 10
   VSIM> force -deposit /reset 0
   

Now press (ModelSim : Run) button couple of times:

You should see simulation results in the wave-window.

You can move signals up and down in the Wave-window with the mouse. You can add signals from different entities to the same wave window by first pointing right entity from structure windown, choosing signal(s) from signal window and then giving command (Signals : View - Wave - Selected signals). Of cource, that is not possible in our trafficlight example (we only have one entity).

After your simulation environment is ready, you can save it in the script file as a configuration for future use by choosing (Wave : File - Save Format...). Saved configuration can be read by choosing (ModelSim : File - Load Format...) and choosing the file you have saved.

You can trace your vhdl source code: First view Source (ModelSim : View - Source) or VSIM> view source and then press (ModelSim : Step) or (ModelSim : Step Over) buttons.

Choose your favorite editor (like emacs) and edit the top level entity (top_level_entity.vhdl):

   ENTITY traffic_lights IS
     PORT ( clk,
            reset             : IN std_logic;
            red_light,
            orange_light,
            green_light       : OUT std_logic);
   END traffic_lights;
   

And then edit the architecture (behavioral.vhdl):

   CASE current_state IS
     WHEN red  =>
       IF (count = 20) THEN
         next_state <= orange;
         count := 0;
         red_light <= '1';
         orange_light <= '0';
         green_light <= '0';
       END IF;
     
     WHEN orange =>
       IF (count = 5) THEN
         next_state <= green;
         count := 0;
         red_light <= '1';
         orange_light <= '1';
         green_light <= '0';
       END IF;
     
     WHEN green =>
       IF (count = 20) THEN
         next_state <= red;
         count := 0;
         red_light <= '0';
         orange_light <= '0';
         green_light <= '1';
       END IF;
     
     WHEN OTHERS =>
         next_state <= current_state;
   END CASE;
   

Now we have to recompile edited VHDL sources before we can simulate our enhanced design. Make will do that for us automatically.

Save changes and goto to the shell prompt and give command:

   % make
   

(Note that if you took a new shell you must first execute your Mentor initialization script and goto the directory where your libraries, codes and Makefile are.)

After compilation you must load new design to the simulator. If you did not Quit the simulator just give the command:

   VSIM> restart -force
   

Otherwise you must start the simulator again:

   % vsim
   

Now you can simulate and verify our new design. Try to view all signals (including those we just added).

5. More Information